SEC KT3170 Low Power CMOS DTMF Receiver DIP18
SEC KT3170 DTMF Receiver
SEC KT3170 Low Power CMOS DTMF Receiver DIP18
Manufactred by SEC - DIP18 through hole package
DESCRIPTION
The KT3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the Switched-Capacitor Filter technology. This LSI consists of band split filters, which seperates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code.
The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV cystal as an external component.
FEATURES
· Detects all 16 standard tones.
· Low power consumption : 15mW (Typ)
· Single power supply : 5V
· Uses inexpensive 3.58MHz crystal
· Three state outputs for microprocessor interface
· Good quality and performance for using in exchange system
· Power down mode/input inhibit
APPLICATIONS PIN CONFIGURATION
· PABX
· Central Office
· Paging Systems
· Remote Control
· Credit Card Systems
· Key Phone System
· Answering Phone
· Home Automation System
· Mobile Radio
· Remote Data Entry
PIN DESCRIPTION
| Pin No | Symbol | Description |
| 1 | IN + | Non inverting input of the op amp. |
| 2 | IN - | Inverting input of the op amp. |
| 3 | GS Gain Select | The output used for gain adjustment of analog input signal with a feedback resistor. |
| 4 | VREF | Reference Voltage output (VDD/2, Typ) can be used to bias the op amp input of VDD/2. |
| 5 | IIN | Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. |
| 6 | PDN | Control input for the stand-by power down mode. Power down occurs when the signal on this input is in high states. This pin is pulled down internally |
| 7 | OSC1 | Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. |
| 8 | OSC2 | Also, external clock can be used. |
| 9 | GND | Ground pin. |
| 10 | OE | Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. |
| 11 | Q1 | Three state data output. When enabled by OE, these digital outputs |
| 12 | Q2 | provide the hexadecimal code corresponding to the last valid tone |
| 13 | Q3 | pair received. |
| 14 | Q4 | |
| 15 | DSO | Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH. |
| 16 | ESO | Early Steering Outputs. Indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low. |
| 17 | SI/GTO | Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI |
| 18 | VDD | Power Supply (+5V, Typ) |